After getting a basic ALU design done yesterday & starting a **very** rough start at a microcodeish thing, today the first design of the controlunit & overall cpu design comes together, so it can actually calculate an addition from two arbitary registers and store the result back into a register of choice! :3

Still a lot to go but excited it works already somewhat! #hardware #fantasyconsole #diy #verilog #systemverilog #software #cpudesign #hardwaredesign #fpga #fpgadev

#cocotb, a #freesoftware cosimulation testbench environment for verifying #VHDL and #SystemVerilog #RTL using #Python, is part now of #guixscience channel. It may be used as any other #guix package with a simple

guix install python-cocotb

This means too that pre-built substitutes are available online .

It's pretty cool that my post on combinational logic in ROHD is in the top-3 results on Google when you search for `always_comb`! https://intel.github.io/rohd-website/blog/combinational-ssa/ #rohd #always_comb #SystemVerilog #dart #opensource

Want to try contributing to an #opensource project? silver is a #SystemVerilog project that has open issues. Check out this issue on GitHub: https://github.com/melt-umn/silver/issues/864

Want to try contributing to an #opensource project? silver is a #SystemVerilog project that has open issues. Check out this issue on GitHub: https://github.com/melt-umn/silver/issues/864